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ddp 3300 a single-chip displa y and deflection processor edition j une 19, 1996 6251-421-1pd preliminar y d a t a sheet m i c r o n a s i n t e r m e t a l l
preliminary data sheet ddp 3300 a micronas intermetall 2 contents page section title 4 1. introduction 4 1.1. system architecture 5 1.2. ddp applications 6 1.3. digital video interfaces 6 1.3.1. picture bus interface 6 1.3.2. digital osd interface 6 1.3.3. priority interface 7 2. functional description 7 2.1. display part 7 2.1.1. luma input 7 2.1.2. luma contrast adjustment 7 2.1.3. black level expander 8 2.1.4. dynamic peaking 9 2.1.5. digital brightness adjustment 9 2.1.6. soft limiter 9 2.1.7. chroma input 9 2.1.8. chroma interpolation 10 2.1.9. chroma transient improvement 10 2.1.10. inverse matrix 10 2.1.11. rgb processing 10 2.1.12. osd color lookup table 10 2.1.13. picture frame generator 11 2.1.14. priority codec 11 2.1.15. scan velocity modulation 11 2.1.16. display phase shifter 13 2.2. analog back end 13 2.2.1. crt measurement and control 14 2.2.2. scart output signal 14 2.2.3. average beam current limiter 17 2.3. synchronization and deflection 17 2.3.1. deflection processing 18 2.3.2. horizontal phase adjustment 19 2.3.3. vertical and east/west deflection 19 2.3.4. protection circuitry 19 2.3.5. deflection bus 20 2.4. reset and standby functions 20 2.4.1. standby mode for vpc and ddp 20 2.4.2. ddp power on 21 2.4.3. ddp standby on/off 21 2.4.4. reset ddp 22 3. serial interface 22 3.1. i 2 c-bus interface 22 3.2. control and status registers
preliminary data sheet ddp 3300 a micronas intermetall 3 contents, continued page section title 29 4. specifications 29 4.1. outline dimensions 30 4.2. pin connections and short descriptions 32 4.3. pin descriptions (pin numbers for plcc68) 34 4.4. pin configuration 36 4.5. pin circuits 38 4.6. electrical characteristics 38 4.6.1. absolute maximum ratings 38 4.6.2. recommended operating conditions 38 4.6.3. characteristics 38 4.6.4. general characteristics 39 4.6.5. bus inputs: luma, chroma, osd, front sync 39 4.6.6. 20.25 mhz main clock input, internally ac coupled 40 4.6.7. 5 mhz clock input 40 4.6.8. i 2 c-bus interface 40 4.6.9. reset input, test input 41 4.6.10. serial deflection interface 42 4.6.11. priority bus input 42 4.6.12. horizontal flyback input 42 4.6.13. main sync output 43 4.6.14. combined sync output 43 4.6.15. horizontal drive output 43 4.6.16. vertical protection input 43 4.6.17. vertical safety input 44 4.6.18. vertical and east/west drive output 44 4.6.19. sense a/d converter input 45 4.6.20. analog rgb and fb inputs 46 4.6.21. analog rgb outputs, d/a converters 48 4.6.22. dac reference, beam current safety 48 4.6.23. scan velocity modulation output 52 5. data sheet history
preliminary data sheet ddp 3300 a micronas intermetall 4 ddp 3300 a, display and deflection processor 50/60 hz (68-pin plcc or 64-pin psdip package) note: revision bars indicate significant changes to the pre- vious version, ed. 6251-421-1ai, advance information, dated feb. 9, 1996. 1. introduction the ddp 3300 a is a single-chip digital display and deflection processor in 0.8 m m cmos technology for high quality back-end applications in 50/60 hz tv sets with 4:3 or 16:9 picture tubes. it can be combined with members of the digit 3000 ic family (vpc 3200 a, vpc 3201 b, tpu 3040) or it can be used with third par- ty products. one ic contains the entire video component and deflection processing and forms the heart of a mod- ern color tv. its performance and complexity allow the user to standardize his product development. hardware and software applications can profit from the modularity, as well as manufacturing, system support or mainte- nance. the main features are single 5 v power supply low cost, high performance all digital video processing black-level expander dynamic peaking soft limiter (gamma correction) color transient improvement programmable rgb matrix scan velocity modulation output picture frame generator additional analog rgb/fastblank input prio interface various digital interfaces high performance h/v deflection separate adc for tube measurements 1.1. system architecture open architecture is the key word to the new dsp gener- ation. flexible standard building blocks have been de- fined that offer continuity and transparency of the entire system. two main modules were defined: video processor and display and deflection processor. they were designed as separate ics. their partitioning permits a variety of ic configurations with the aim to sat- isfy the particular requirements of different applications. both, analog and digital interfaces, support state-of-the art tv receivers as well as other environments. fig. 11 shows the block diagram of the single-chip display and deflection processor. y features ycrcb 4:2:2 h/v deflection c features rgb prio rgb switch dig. scan vel. mod. rgb switch analog rgb out rgb/ fbl in hflyb. v & e/w hdrive svm digital rgb matrix color lookup table i 2 c interface sda, scl 3 x dac (10 bit) and tube control dacs sense input range switch 1 & 2 fpdat front sync main sync timing generator fig. 11: display and deflection processor measu- rement adc
preliminary data sheet ddp 3300 a micronas intermetall 5 1.2. ddp applications fig. 12 depicts several ddp applications. since the ddp functions as a video back-end, it must be complemented with additional functionality to form a complete tv set. the ddp 3310 b will be a further development of the ddp 3300 a. it is targeted for a system with a horizontal frequency of 32 khz and a vertical frequency of 100 or 120 hz. the vpc3210a/3211b processes all worldwide analog video signals (including the european palplus) and al- lows nonlinear panorama aspect ratio conversion. thus 4:3 and 16:9 systems can easily be configured by soft- ware. the aspect ratio scaling is also used as a sample rate converter to provide a line-locked digital component output bus (ycrcb) compliant to itur601. all video processing and line-locked clock/data generation is derived from a single 20.25 mhz crystal. an optional adaptive 2-line combfilter (vpc3211b) performs y/c separation for pal and ntsc and all of their substan- dards. both versions of the vpc are plug-in compatible. the cip 3250 a provides a high-quality analog rgb in- terface with character insertion capability. this allows appropriate processing of external sources such as mpeg2 set-top boxes in transparent (4:2:2) quality. fur- thermore, it translates rgb/fastblank signals to the common digital video bus and makes those signals available for 100 hz processing. in some european countries (italy), this feature is mandatory. the ip indicates memory based image processing, such as scan rate conversion, vertical processing (zoom), or pal+ reconstruction. examples: europe: 15 khz /50 hz 32 khz /100 hz interlaced us: 15 khz /60 hz 31 khz /60 hz non-interlaced note that the vpc supports memory based applications through line-locked clocks, syncs, and data. cip may run either with the native digit3000 clock but also with a line-locked clock system. rgb cvbs cip 3250a h/v defl. ip rgb ddp 3300a cvbs vpc 320x h/v defl. combfilter 16:9 video scan vel. mod. pal+ 100 hz rgb rgb rgb saturation fastbl. mixing ip fig. 12: ddp 3300 a applications vpc 321x ddp 3310b
preliminary data sheet ddp 3300 a micronas intermetall 6 1.3. digital video interfaces the digital video interface allows input of digital data in yc r c b format on the yc r c b data bus. the orthogonal data structure of this bus is the ideal interface point to ex- ternal data sources and sinks. furthermore, a host of formats are supported, e.g. support of level-2 teletext or the priority pixel bus concept. figure 13 shows all available digital interfaces: yc r c b 16 bit 4:2:2 osd 5 bit 4:4:4 prio 3 bit, source selection the ycrcb bus is used for video input. the osd inter- face is used for insertion of a teletext or osd picture. the priority bus allows to mix up to 8 sources on the yc r c b /osd bus. ycrcb prio osd pip tpu ccu/ osd ddp 3300a display and deflection processor fig. 13: ddp video interfaces vpc 1.3.1. picture bus interface the video bus the video bus format between all digit3000 ics is ycrcb with 20.25 msamples/s. only active video is transferred, synchronized by the system main sync sig- nal (msy), which indicates the start of valid data for each scan line. the number of active samples per line is 1080 for all standards (525 and 625). via the msy line, serial data is transferred which con- tains information on the main picture, such as current line number, odd/even field etc. it is generated by the deflection circuitry and represents the orthogonal time- base for the entire system. feature ics (e.g. pip) will be synchronized to the main yc r c b bus. digital insertion (boxing) is controlled by a priority system. 1.3.2. digital osd interface digital osd from text or on-screen-display is connected via the picture bus. the osd signal is 5 bits wide. the osd signals are not subject to any post-filtering. the osd signal provides 3-bit rgb (one bit per color), the 4th bit allows to display of half contrast colors. the 5 th bit enables a programmable color-look-up table with 16 en- tries and 4-bit resolution per color. this allows the sup- port of a world system teletext level-2 color display. dis- play contrast for osd data can be adjusted separately by three contrast multipliers. 1.3.3. priority interface up to eight digital yc r c b or osd sources (main decoder, pip, osd, text, etc.) may be selected in real-time by means of a 3-bit priority bus. thus, a pixelwise bus arbi- tration and source switching is possible. it is essential that all yc r c b -sources are synchronous and orthogonal. in general, each source ( master) has its own yc r c b bus request. this bus request may either be software or hardware-controlled, i.e. by a fast blank signal. data col- lision is avoided by a bus arbiter that provides the indi- vidual bus acknowledge in accordance to a user-defined priority. each master sends a bus request with his individual priority id onto the prio-bus and immediately reads back the bus status. only in case of positive arbitration (send- prio-id read-prio-id) the bus acknowledge becomes active and the data is sent. this treatment has many features that have impact on the appearance of a tv picture: real-time bus arbitration (pip, osd...) priority configuration by software different coefficients for different sources
preliminary data sheet ddp 3300 a micronas intermetall 7 2. functional description 2.1. display part in the display part the conversion from digital yc r c b to analog rgb is carried out. a block diagram is shown in figure 29. in the luminance processing, path contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. in the chrominance path, the c r c b signals are converted to 20.25 mhz sampling rate and filtered by a color transient improvement circuit. the yc r c b signals are converted by a programmable matrix to rgb color space. the signals inserted via the yc r c b bus are identified by their respective priority. the display processor provides separate control settings for two pictures, i.e. different coefficients for a `main' and a `side' picture. the digital osd insertion circuit allows the insertion of a 5-bit osd signal. the color space for this signal is con- trolled by a partially programmable color look-up table (clut) and contrast adjustment. the osd signals and the display clock are synchronized to the horizontal flyback. for the display clock, a gate delay phase shifter is used. in the analog backend, three 10-bit digital-to-analog converters provide the analog output signals. 2.1.1. luma input the luminance input is 8 bit wide. if noise shaping was applied to the luminance signal, a notch filter for an lsb shaping signal at 10.125 mhz reconstructs the real lsb. this increases the signal resolution to 9-bit data. the vpc 32xx a supports this noise shaping. after this filter (gain 2) from the 9-bit signal an offset of 32 is subtracted to shift the black level to zero. this as- sumes the black level of the input signal to be at 16 (itur 601 standard). 2.1.2. luma contrast adjustment the 9-bit luminance signal is multiplied by a factor of 0 ... 2 in 64 steps. an 11-bit output signal is used to in- crease the accuracy of the luma signal. the contrast can be adjusted separately for main picture and side picture. 2.1.3. black level expander the black level expander enhances the contrast of the picture. therefore the luminance signal is modified with an adjustable, non-linear function. dark areas of the pic- ture are changed to black, while bright areas remain un- changed. the advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. the black level expander works adaptively. depending on the measured amplitudes `l min ' and `l max ' of the low- pass-filtered luminance and an adjustable coefficient btlt, a tilt point `l t ' is being established by l t = l min + btlt ( l max l min ). above this value there is no expansion, while all lumi- nance values below this point are expanded according to: l out = l in + bam (l in l t ) a second threshold, l tr , can be programmed, above which there is no expansion. the characteristics of the black level expander are shown in fig. 21 and fig. 22. the tilt point l t is a function of the dynamic range of the video signal. thus, the black level expansion is only per- formed when the video signal has a large dynamic range. otherwise, the expansion to black is zero. this al- lows the correction of the characteristics of the picture tube. l in l out l min l max l t l tr fig. 21: characteristics of the black level expander l tr bam bthr btlt a) l min l max l t l t b) fig. 22: black-level-expansion a) luminance input b) luminance input and output
preliminary data sheet ddp 3300 a micronas intermetall 8 2.1.4. dynamic peaking especially with decoded composite signals and notch fil- ter luminance separation, as input signals, it is neces- sary to improve the luminance frequency characteris- tics. with transparent, high-bandwidth signals, it is sometimes desirable to soften the image. in the ddp 3300 a, the luma response is improved by `dynamic' peaking. the algorithm has been optimized regarding step and frequency response. it adapts to the amplitude of the high frequency part. small ac ampli- tudes are processed, while large ac amplitudes stay nearly unmodified. the dynamic range can be adjusted from 14 to 14 db for small high frequency signals. there is sepa- rate adjustment for signal overshoot and for signal un- dershoot. for large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. the peaking can be switched over to asofteningo by inverting the peaking term by software. the center frequency of the peaking filter is switchable from 2.5 mhz to 3.2 mhz. for s-vhs and for notch filter color decoding, the total system frequency responses for both pal and ntsc are shown in figure 24. transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. fig. 23: dynamic peaking frequency response db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 cf= 3.2 mhz cf= 2.5 mhz s-vhs db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 cf= 3.2 mhz cf= 2.5 mhz pal/secam db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 db mhz 20 5 5 10 15 20 02 4 68 10 15 10 0 cf= 2.5 mhz cf= 3.2 mhz fig. 24: total frequency response for peaking filter and s-vhs, pal, ntsc ntsc
preliminary data sheet ddp 3300 a micronas intermetall 9 2.1.5. digital brightness adjustment the dc-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. with a contrast adjustment of 32 (gain 1) the signal can be shifted by 100%. after the brightness addition, the negative going signals are limited to zero. it is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. the digital brightness adjustment is separate for main and side picture. 2.1.6. soft limiter the dynamic range of the processed luma signal must be limited to prevent the crt from overload. an appro- priate headroom for contrast, peaking and brightness can be adjusted by the tv manufacturer according to the crt characteristics. all signals above this limit will be `soft'-clipped. a characteristic diagram of the soft limiter is shown in fig. 25. the total limiter consists of three parts: part 1 includes adjustable tilt point and gain. the gain before the tilt value is 1. above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. therefore the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. the tilt value can be adjusted from 0 to 511. part 2 has the same characteristics as part 1. the sub- tracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input sig- nal is above the both tilt values (see characteristics). finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. fig. 25: characteristic of soft limiter a and b and hard limiter output limiter input 0 2 4 6 8 12 10 0 2 4 6 8 10 12 14 14 slope 1 [0...15] slope 2 [0...15] part 1 part 2 hard limiter tilt 1 [ 0...511] tilt 2 [0...511] range= 256...511 0 511 0 1023 calculation example for the softlimiter input amplitude. (the real signal processing in the limiter is 2 bit more than described here) y input 16...235 (itur) contrast 63 dig. brightness 20 ble off peaking off limiter input signal: (yinblack level)contr./32 + brightn. (23516) 63/32 + 20 = 451 black level 16 (constant) 100 200 300 400 500 600 700 800 900 100 200 300 400 2.1.7. chroma input the chroma input signal is typically a multiplexed c r and c b signal in 8-bit two's complement code. it can be switched between normal or inverted signal and be- tween two's complement or binary offset (straight binary) code. also the delay can be adjusted in 5 steps within a range of 2 clock periods. 2.1.8. chroma interpolation a linear phase interpolator is used to convert the chroma sampling rate from 10.125 mhz (4:2:2) to 20.25 mhz (4:4:4). the frequency response of the interpolator is shown in fig. 26. all further processing is carried out at the full sampling rate. db mhz 0 10 20 30 40 50 02 4 68 10 fig. 26: frequency response of the chroma interpolation filter
preliminary data sheet ddp 3300 a micronas intermetall 10 2.1.9. chroma transient improvement the intention of this block is to enhance the chroma resolution. a correction signal is calculated by differenti- ation of the color difference signals. the differentiation can be selected according to the signal bandwidth, e.g. for pal/ntsc/secam or digital component signals, respectively. the amplitude of the correction signal is adjustable. small noise amplitudes in the correction sig- nal are suppressed by an adjustable coring circuit. to eliminate `wrong colors', which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automati- cally. fig. 27: digital color transient improvement t t t cr out cb out ampl. cr in cb in a) b) c) a) cr cb input of dti b) cr cb input correction signal c) sharpened and limited cr cb 2.1.10. inverse matrix a 6-multiplier matrix transcodes the cr and cb signals to ry, by, and gy. the multipliers are also used to adjust color saturation in the range of 0 to 2. the coeffi- cients are signed and have a resolution of 9 bits. there are separate matrix coefficients for main and side pic- tures. the matrix computes: ry mr1*cb mr2*cr gy mg1*cb mg2*cr by mb1*cb mb2*cr the initialization values for the matrix are computed from the standard itur (ccir) matrix: r g b 1 1 1 0 0.345 1.773 1.402 0.713 0 y cb cr for a contrast setting of ctm 32, the matrix values are scaled by a factor of 64, see also table 31. 2.1.11. rgb processing after adding the post-processed luma, the digital rgb signals are limited to 10 bits. three multipliers are used to digitally adjust the white drive. using the same multi- pliers an average beam current limiter is implemented. see also section 2.2.1. `crt measurement and con- trol'. 2.1.12. osd color lookup table the ddp 3300 a has five input lines for an osd signal. this signal forms a 5-bit address for a color look-up table (clut). the clut is a memory with 32 words where each word holds a rgb value. bits 0 to 3 (bit 4 0) form the addresses for the rom part of the osd, which generates full rgb signals (bit 0 to 2) and half-contrast rgb signals (bit 3). bit 4 addresses the ram part of the osd with 16 freely programmable colors, addressable with bit 0 to 3. the programming is done via the i 2 c-bus. the amplitude of the clut output signals can be ad- justed separately for r, g and b via the i 2 c-bus. the switchover between video rgb and osd rgb is done via the priority bus. 2.1.13. picture frame generator when the picture does not fill the total screen (height or width too small) it is surrounded with black areas. these areas (and more) can be colored with the picture frame generator. this is done by switching over the rgb signal from the matrix to the signal from the osd color look-up table.
preliminary data sheet ddp 3300 a micronas intermetall 11 the width of each area (left, right, upper, lower) can be adjusted separately. the generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. this means, it runs during horizontal, respectively vertical flyback. the color of the complete border can be stored in the programmable osd color look-up table in a separate address. the format is 3 4 bit rgb. the contrast can be adjusted separately. the picture frame generator includes a priority master circuit. its priority is programmable and the border is generated only if the priority is higher than the priority at the prio bus. therefore the border can be underlay or overlay depending on the picture source. 2.1.14. priority codec the priority decoder has three input lines for up to eight priorities. the highest priority is all three lines at low lev- el. a 5-bit information is attached to each priority (see table 31 `priority bus'). these bits are programmable via the i 2 c-bus and have the following meanings: one of two contrast, brightness and matrix values for main and side picture rgb from video signal or color look-up table disable/enable black level expander disable/enable peaking transient suppression when signal is switched disable/enable analog fast blank 2.1.15. scan velocity modulation the rgb input signal of the svm is converted to y in a simple matrix. then the y signal is differentiated by a fil- ter of the transfer function 1z n , where n is program- mable from 1 to 6. with a coring, some noise can be sup- pressed. this is followed by a gain adjustment and an adjustable limiter. the analog output signal is generated by an 8-bit d/a converter. the signal delay can be adjusted by 3.5 clocks in half- clock steps. for the gain and filter adjustment there are two parameter sets. the switching between these two sets is done with the same rgb switch signal that is used for switching between videorgb and osdrgb for the rgb outputs. (see fig. 28). fig. 28: svm block diagram g rb matrix and shaping modulation notch differen- tiator 1z nx n1 n2 coring adjustment gain adjustment limiter delay adjustment d/a converter coring gain1 gain2 limit delay rgb switch output 2.1.16. display phase shifter a phase shifter is used to partially compensate the phase differences between the video source and the fly- back signal. by using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. it has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 mhz. the large amount of phase shift (full clock periods) is realized in the front-end circuit.
preliminary data sheet ddp 3300 a micronas intermetall 12 contrast dynamic peaking brightness + offset softlimiter whitedrive measurement clock horizontal flyback dti (cr) dti (cb) interpol 4:4:4 black level expander 10 dig. rout dig. gout dig. bout cr cb dig. y in dig. crcb in 8 8 matrix saturation whitedrive r x beamcurr. lim. display & clock control prio in prio decoder select coefficients main picture side picture 3 matrix r' matrix g' matrix b' y r g b luma insert for crtmeasurement clut, for crtmeasurement blanking fig. 29: display part dig. osd in 5 contrast svmout 10 10 scan velocity modulation picture frame generator prio prio whitedrive g x beamcurr. lim. whitedrive b x beamcurr. lim. phase shift 0...1 clock phase shift 0...1 clock phase shift 0...1 clock
preliminary data sheet ddp 3300 a micronas intermetall 13 2.2. analog back end the digital rgb signals are converted to analog rgbs using three video digital to analog converters (dac) with 10-bit resolution. an analog brightness value is provided by three additional dacs. the adjustment range is 40% of the full rgb range. the back-end allows insertion of an external analog rgb signal. the rgb signal is key-clamped and in- serted into the main rgb by the fast blank switch. the external rgb signals are virtually handled as priority bus signals. thus, they can be overlaid or underlaid to the digital picture. the external rgb signals can be ad- justed independently as regards dc-level (brightness) and magnitude (contrast). controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the fast processor, located in the vpc 3200 a (ref 2.3.5.). control of the cutoff dacs is via i 2 c-bus reg- isters. finally cutoff and blanking values are added to the rgb signals. cutoff (dark current) is provided by three 9-bit dacs. the adjustment range is 60% of full scale rgb range. the analog rgb-outputs are current outputs with cur- rent-sink characteristics. the maximum current drawn by the output stage is obtained with peak white rgb. 2.2.1. crt measurement and control the display processor is equipped with an 8-bit pdm- adc for all measuring purposes. the adc is connected to the sense input pin, the input range is 0 to 1.5v. the bandwidth of the pdm filter can be selected; it is 40/80 khz for small/large bandwidth setting. the input impedance is more than 1 m w . cutoff and white drive current measurement are carried out during the vertical blanking interval. they always use the small bandwidth setting. the current range for the cutoff measurement is set by connecting a sense resis- tor to the madc input. for the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (rsw2). during the ac- tive picture, the minimum and maximum beam current is measured. the measurement range can be set by us- ing the range select switch 1 pin (rsw1) as shown in fig. 210 and fig. 211. the timing window of this mea- surement is programmable. the intention is to automati- cally detect letterbox transmission or to measure the ac- tual beam current. all control loops are closed via the external control microprocessor. sense rsw1 rsw2 r2 r3 beam current a d madc r1 fig. 210: madc range switches ultra black black cutoff white drive cr + ibrm cr + ibrm + wdrvwdr r g b tml cg + ibrm cb + ibrm picture meas. picture meas. tube measurement active measure- ment resistor r1 r2 r3 rsw1=on, rsw2=on r1 r1 r3 rsw2 r r cutoff cutoff g b r1 r2 r3 fig. 211: madc measurement timing rsw1=on, rsw2=on remark: the adjustment for ibrm, wdr, wdg, wdb is done in the vpc 3200 a pmst pmso =on lines
preliminary data sheet ddp 3300 a micronas intermetall 14 in each field two sets of measurements can be taken: a) the picture tube measurement returns results for cutoff r cutoff g cutoff b white drive r or g or b (sequentially) b) the picture measurement returns data on active picture maximum current active picture minimum current the tube measurement is automatically started when the cutoff blue result register is read. cutoff control for rgb requires one field only while a complete white-drive control requires three fields. if the measurement mode is set to `offset check', a measurement cycle is run with the cutoff/whitedrive signals set to zero. this allows to compensate the madc offset as well as input the leakage currents. during cutoff and whitedrive measure- ments, the average beam current limiter function (ref. 2.2.3.) is switched off and a programmable value is used for the brightness setting. the start line of the tube mea- surement can be programmed via i 2 c-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. the picture measurement must be enabled by the con- trol microprocessor after reading the min./max. result registers. if a `1' is written into bit 2 in subaddress 25, the measurement runs for one field. for the next measure- ment a `1' has to be written again. the measurement is always started at the beginning of active video. the vertical timing for the picture measurement is pro- grammable, and may even be a single line. also the sig- nal bandwidth is switchable for the picture measure- ment. two horizontal windows are available for the picture measurement. the large window is active for the entire active line. tube measurement is always carried out with the small window. measurement windows for picture and tube measurement are shown in figure 212. active video field 1/ 2 small window for tube measurement (cutoff, white drive) large window for active picture picture meas. start tube measurement picture meas. end fig. 212: windows for tube and picture measure- ments 2.2.2. scart output signal the rgb output of the ddp 3300 a can also be used to drive a scart output. in the case of the scart signal, the parameter clmpr (clamping reference) has to be set to 1. then, during blanking, the rgb outputs are au- tomatically set to 50% of the maximum brightness. the dc offset values can be adjusted with the cutoff parame- ters cr, cg, and cb. the amplitudes can be adjusted with the drive parameters wdr, wdg, and wdb (lo- cated in the vpc 3200 a). 2.2.3. average beam current limiter the average beam current limiter (bcl) uses the sense input for the beam current measurement. the bcl uses a different filter to average the beam current during the active picture. the filter bandwidth is approx. 2 khz. the beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measure- ment line. the beam current limiter function is located in the vpc 32xx a. the data exchange between the vpc and the ddp is done via a single-wire serial interface (ref. section 2.3.5.). the beam current limiter allows the setting of a threshold current. if the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the rgb outputs by adjusting the white-drive multipliers for the internal (digital) rgb signals, and the analog con- trast multipliers for the analog rgb inputs, respectively.
preliminary data sheet ddp 3300 a micronas intermetall 15 the lower limit of the attenuator is programmable, thus a minimum contrast can always be set. during the tube measurement, the abl attenuation is switched off. after the white drive measurement line it takes 3 lines to switch back to bcl limited drives and brightness. typical characteristics of the abl for different loop gains are shown in fig. 213; for this example the tube has been assumed to have square law characteris- tics. fig. 213: beam current limiter characteristics: beam current output vs. drive bcl threshold: 1 beam current drive
preliminary data sheet ddp 3300 a micronas intermetall 16 ext. contrast * cutoff r 10 bit dac video 3.75ma blank & timing 8 bit adc measurm. 9 bit u/idac 3.75ma clamp key analog r in sense analog r out analog g out analog b out analog g in analog b in measurement buffer digital r in h v measurem. 10 9 bit dac 1.5 ma digital g in digital b in 9 bit dac 2.2 ma 10 bit dac video 3.75ma 10 bit dac video 3.75ma 9 bit u/idac 3.75ma clamp 9 bit u/idac 3.75ma clamp cutoff g 9 bit dac 2.2 ma cutoff b 9 bit dac 2.2 ma 9 bit dac 1.5 ma 9 bit dac 1.5 ma input ext. brightness * i/o fig. 214: analog back-end white drive r * white drive r ext. brightness * white drive g ext. brightness * white drive b 9 bit dac 1.5 ma white drive g 9 bit dac 1.5 ma int. brightness * white drive b 9 bit dac 1.5 ma white drive r int. brightness * int. brightness * fast blank in beam current lim. ext. contrast * white drive g * beam current lim. ext. contrast * white drive b * beam current lim. white drive r white drive g white drive b int . brightness ext. contrast ext. brightness 10 10 analog svm out 8 8 bit dac svm 1.88ma 0.94ma digital svm in 750 m a blanking 750 m a blanking 750 m a blanking vpc 3200a serial interface
ddp 3300 a preliminary data sheet micronas intermetall 17 2.3. synchronization and deflection the synchronization and deflection processing is distributed over front-end, e.g., the vpc 320x and the ddp 3300 a back end. the video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front end. most of the processing that runs at the horizontal frequency is pro- grammed on the internal fast processor (fp). also the values for vertical & east/west deflection are calculated by the fp software. the information extracted by the video sync processing is multiplexed onto the hardware front sync signal (fsy) and distributed to the rest of the video processing sys- tem. the format of the front sync signal is given in fig. 215. the data for the vertical deflection, the sawtooth and the east/west correction signal is calculated in the vpc 320x. the data is transferred to the back-end by a single wire interface. the display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of hori- zontal and vertical drive to the video timing extracted in the front-end, are implemented in hardware in the back- end. f1 (not in scale) input analog video fsy f1 parity v: vert. sync 0 = off 1 = on f: field # 0 = field 1 1 = field 2 h: helper fig. 215: front sync format f0 skew msb skew lsb fv f0: reserved h 2.3.1. deflection processing the deflection processing generates the signals for the horizontal and vertical drive (see fig. 216). this block contains two phase-locked loops: pll2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. phase and frequency are synchronized by the front sync signal. pll3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. phase and frequency are synchronized by the oscillator signal of pll2. the horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. the generator runs at 1 mhz; in the output stage the frequency is divided down to give drive-pulse period and width. in standby mode, the output stage is driven from an internal 1 mhz clock that is derived from the 5 mhz clock input signal and a fixed drive pulse width is used. when the circuit is switched out of standby operation the drive pulse width is programmable. the horizontal drive uses a high voltage (8v) open drain out- put transistor. the main sync (msy) signal that is generated from pll3 is a multiplex of all display-related data (fig. 217). this signal is intended for use by other pro- cessors, e.g. a pip processor can use this signal to ad- just to a certain display position.
ddp 3300 a preliminary data sheet micronas intermetall 18 phase comparator & lowpass pll2 composite sync generator e/w correction sawtooth pwm 15 bit csy e/w ouput v output v flyback pwm 15 bit dco front sync interface fsy vdata main sync generator vertical serial data phase comparator & lowpass pll3 1:64 & output stage h flyback h drive dco display timing line counter blanking, clamping, etc. clock & control sinewave generator & dac lpf standby clock fig. 216: deflection processing block diagram msy vertical reset skew measure ment m1 m2 (not in scale) m1 m2 f v line [0] line [7] line [8] not used parity input analog video msy not used not used not used not used timing reference for picture bus chroma multiplex sync active picture data after xxx clocks v: vert. blanking 0 = off 1 = on f: field # 0 = field 1 1 = field 2 line: field line # 1...n parity fig. 217: main sync format 2.3.2. horizontal phase adjustment this section describes a simple way to align pll phases and the horizontal frame position. 1. the parameter newlin in the vpc 320x has to be adjusted. the minimum possible value is 34 (recom- mended for a standard 4:3 signal). 2. with hdrv, the duration of the horizontal drive pulse has to be adjusted. 3. with pofs2, the clamping pulse for the analog rgb input has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 4. with pofs3, the horizontal position of the analog rgb signal (from scart) has to be adjusted. 5. with hpos, the digital rgb output signal (from vpc) has to be adjusted to the correct horizontal position. 6. with hbst and hbso, the start and stop values for the horizontal blanking have to be adjusted.
ddp 3300 a preliminary data sheet micronas intermetall 19 2.3.3. vertical and east/west deflection the calculations of the vertical and east/west deflection waveforms are done in the video front-end, i.e., the vpc 320x. the algorithm uses a chain of accumulators to generate the required polynomial waveforms. to pro- duce the deflection waveforms, the accumulators are initialized at the beginning of each field. the initialization values must be computed by the tv control processor and are written to the vpc 320x once. the waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. p: a + b (x0.5) + c (x0.5) 2 + d (x0.5) 3 + e (x0.5) 4 the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east/west deflection are 12-bit values. the vertical waveform can be scaled according the average beam current. this is used to compensate the effects of electric high tension changes due to beam cur- rent variations. in order to get a faster vertical retrace timing, the output impedance of the vertical d/a-converter can be reduced by 50% during the re- trace. fig. 218 shows some vertical and east/west deflection waveforms. the polynomial coefficients are also stated. detailed information on the programming of the vertical and east/west deflection parameters is given in the vpc 320x datasheet. fig. 218: vertical and east/west deflection waveforms vertical: a,b,c,d 0,1,0,0 east/west: a,b,c,d,e 0,0,1,0,0 0,1,1,0 0,0,0,0,1 0,1,0,1 0,0,1,1,1 2.3.4. protection circuitry picture tube and drive stage protection is provided through the following measures: vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the rgb drive signals are blanked. drive shutoff during flyback: this feature can be se- lected by software. safety input pin: this input has two thresholds. be- tween zero and the lower threshold, normal function- ing takes place. between the lower and the higher threshold, the rgb signals are blanked. above the higher threshold, the rgb signals are blanked and the horizontal drive is shut off. both thresholds have a small hysteresis. the main oscillator (not included in the ddp ) and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the tv set is powering up. 2.3.5. deflection bus the deflection bus is a serial, bidirectional interface be- tween the ddp and the fast processor in the vpc chip, so the calculation of the vertical and the east/west sig- nals is performed by the fp in the vpc. the fp in the vpc also does the beam current limitation. the follow- ing data is transferred via the deflection bus: vertical and east/west drive values for the vert and ew dac from vpc to ddp values for r/g/b dacs for ext. brightness, internal brightness, external contrast, white drive from vpc to ddp tube current measurement from ddp to vpc status bits from ddp to vpc vertical reset of deflection back-end (from vpc to ddp).
ddp 3300 a preliminary data sheet micronas intermetall 20 2.4. reset and standby functions reset of most functions (exceptions see below) is per- formed by a reset pin. when this pin becomes active, all the internal registers and counters are set to zero. when this pin is released, the internal reset is still active for approximately 4 m s. after that time all the internal regis- ters are loaded with the values defined in the defaults rom. all the registers which are updated with the verti- cal sync get these values with the next vertical sync. during this initialization procedure (approx. 60 m s) it is not possible to access the ddp via the serial interface (i 2 c). access to other ics via the serial bus is possible during that time. the same initialization procedure is started when the internal clock supervision detects that there is no clock (in the video processing part). exceptions for initialization : ccu clock divider (5mhz), not initialized by reset standby clock divider (1mhz), not initialized by reset, but clock selector switched to standby clock during standby, only the horizontal drive pulse and the 5 mhz clock output for the control microprocessor are active. the standby circuitry is reset when the standby supply voltage is applied. 2.4.1. standby mode for vpc and ddp in a system with the video processor vpc and the dis- play processor ddp it is possible to realize a standby mode where the whole signal processing is disabled and only some basic functions are working. this is possible because different supply pins for normal operation and standby operation are available. the standby mode is realized by switching off the supplies for analog frontend (vsupf), analog backend (vsupo) and the normal dig- ital supply (vsupd). the standby supply (vstdby) still has its nominal voltage. in the standby mode, all regis- ters and counter values in the vpc and ddp are lost, they have to be re-initialized after analog and digital sup- plies are switched on again. the vpc still generates the 5 mhz clock which is used in the ddp as timing reference during standby. clk5 clk20 vpc ddp vstdby vsupd vsupf vstdby vsupd vsupo vstby vsup reset fig. 219: vpc & ddp supply and clock gndd gndf gndd gndo to disable all the analog and digital functions, it is neces- sary to bring the analog and digital supplies below 0.5 v. only this guarantees that all the normal functions are disabled and the standby current for analog and digital supply is at its minimum. in the standby mode the following functions are still available : crystal oscillator of vpc 5 mhz clock output of vpc, standby clock for ddp, can also be used as ccu clock horizontal output of ddp, duty cycle set to 50 %, the 5 mhz clock is used as timing reference in standby mode (standby clock); protection modes with safety and horizontal flyback pins (in vpc) are not available when the main power goes down, ddp and vpc react in different ways. an internal power supervision, in both vpc and ddp, generates the required power down sig- nals. 2.4.2. ddp power on the ddp has its own clock and voltage supervision cir- cuit to generate a reset signal during power on. the ini- tialization of registers is described in section 2.4.3. `ddp standby on/off'. the hout signal is disabled until a proper clk5 signal (5 mhz clock) has been detected. therefore at least one positive and negative edge with the correct distance (two 20 mhz clocks) has to be re- ceived. after this clock release signal, the hout generator runs with the standby clock, which is derived from the 5 mhz clock (divide by 5). switching to the line
preliminary data sheet ddp 3300 a micronas intermetall 21 locked clock from the horizontal pll is performed by the ccu. vstby vsupd ~ 50 m s normal mode standby mode internal reset internal oszillator clk5 5 mhz clock clock release hout fig. 220: ddp power on, standby on/off ~ 4 m s normal mode 2.4.3. ddp standby on/off switching the ddp to standby mode is more critical be- cause of the hout output signal. before the standby mode is entered, the clock source for the horizontal out- put generator has to be switched to the standby clock. switching to standby mode can be done by the ccu as a reaction to a remote control command (see register 53, ehpll disable) or by the internal voltage supervision of the ddp. this voltage supervision activates the power down signal when the supply for the digital circuits (vsupd) goes below v supdpd ( 4.5 v). the power down signal switches the clock source for the hout generation to the standby clock and sets the duty factor to 50%. this is exactly what the ehpll bit does. because the clocks from the ddppll and the standby clock are not in phase, the actual phase (high/low) of the hout signal may be up to one pll or standby clock ( 1 m s) longer than a regular one when the clock source is changed. the voltage supervising reacts if vsupd goes below v supdpd for more than 50 ns. this power down signal is extended by 50 m s after vsupd is back again. when switched off, the negative slope of the supply voltage vsupd should not be larger than approximately 0.2 v/ m s (see recommended operating conditions). resetq por update 4 m s 60 m s fig. 221: external reset 2.4.4. reset ddp reset of most functions (exception see below) is per- formed by different sources: power on circuit (vstby, vsupd) reset pin (ddp) voltage superv. 5 mhz clock release clock vstby reset pin reset generator voltage superv. vsupd reset clk5 clk5 observer (to hout gen) fig. 222: ddp reset generation if one of these sources creates a reset, all the internal registers and counters are set to zero. when this reset source becomes inactive, the internal reset is still active for 4 m s. after that time all the internal registers are loaded with the values defined in the defaults rom. all the registers which are updated with the vertical sync (chain registers) get these values with the next vertical sync. during this initialization procedure (approx. 60 m s) it is not possible to access the ddp via the i 2 c-bus.
ddp 3300 a preliminary data sheet micronas intermetall 22 3. serial interface 3.1. i 2 c-bus interface communication between the ddp 3300 a and the ex- ternal controller is done via i 2 c-bus. the ddp 3300 a has an i 2 c-bus slave interface and uses i 2 c clock syn- chronization to slow down the interface if required. the i 2 c-bus interface uses one level of subaddress: one i 2 c- bus address is used to address the ic and a subaddress selects one of the internal registers. the i 2 c-bus chip address is given below: note: the i 2 c address is subject to change! a6 a5 a4 a3 a2 a1 a0 r/w 1 0 0 0 1 0 1 0/1 the registers of the ddp 3300 a have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. functions implemented by firmware in the on-chip con- trol microprocessor (fp) located in the vpc are ex- plained in the vpc datasheet. figure 31 shows i 2 c-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. wp 1 or 2 byte data w high byte data s s ack ack ack ack 0111 1100 0111 1100 r s ack sda scl 1 0 sp p low byte data ack w= 0 r= 1 ack = 0 nak= 1 s = start p = stop ack nak fig. 31: i 2 c-bus protocols 1000 101 1000 101 1000 101 i 2 c read access subaddress 7c example: i 2 c read access subaddress 7c 3.2. control and status registers table 31 gives definitions of the ddp 3300 a control and status registers. the number of bits indicated for each register in the table is the number of bits imple- mented in hardware, i.e., a 9-bit register must always be accessed using two data bytes, but the 7 msb will be don't care on write operations and 0 on read operations. write registers that can be read back are indicated in the following table. a hardware reset initializes all control registers to 0. the automatic chip initialization loads a selected set of regis- ters with the default values given in table 31. the register modes given in table 31 are: w write only register w/r write/read data register r read data from ddp 3300 a h register is latched with horizontal pulse v register is latched with vertical pulse the mnemonics used in the intermetall ddp 3300 a demo software are given in the last column.
ddp 3300 a preliminary data sheet micronas intermetall 23 table 31: control and status registers i 2 c sub address number of bits mode function default name priority bus priority mask register, if bit[x] is set to 1 then the function is active for the respective signal priority 75 9 w v bit [7:0] bit[x] 0/1: select contrast,brightness,matrix for main / side picture 0 pbct 71 9 w v bit [7:0] bit[x] 0/1: select main(video)/external (via clut) rgb 0 pbergb 7d 9 w v bit [7:0] bit[x] 0/1: disable/enable black level expander 0 pbble 79 9 w v bit [7:0] bit[x] 0/1: disable/enable peaking transient suppression when signal is switched 0 pbpk 4b 9 w v bit [7:0] bit[x] 0/1: disable/enable analog fast blank input 0 pbfb 47 9 w v bit [2:0] picture frame generator priority id bit [8] enable prio id for picture frame generator 0 pfgid pfgen luma channel 61 9 w v bit [5:0] 0..63/32 main picture contrast 32 ctm 65 9 w v bit [5:0] 0..63/32 side picture contrast 32 cts 51 9 w v bit [8:0] 256..255 main picture brightness 0 brm 55 9 w v bit [8:0] 256..255 side picture brightness 0 brs 59 9 w v black level expander: bit [3:0] 0..15 tilt coefficient bit [8:4] 0...31 amount 8 12 btlt bam 5d 9 w v black level expander: bit [8:0] 0..511 disable expansion, threshold value 200 bthr 69 9 w v luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) 4 4 0 pkun pkov pkinv 6d 9 w v luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/low 3 0 cor pfs 41 9 w v luma soft limiter, slope a and b bit [3:0] slope segment a bit [7:4] slope segment b 0 0 lslsa lslsb 45 9 w v bit [7:0] luma soft limiter absolute limit (unsigned) bit [8] 0/1 modulation off/on 255 1 lslal lslm 49 9 w v bit [8:0] luma soft limiter segment b tilt point (unsigned) 300 lsltb 4d 9 w v bit [8:0] luma soft limiter segment a tilt point (unsigned) 250 lslta
ddp 3300 a preliminary data sheet micronas intermetall 24 name default function mode number of bits i 2 c sub address chroma channel 14 8 w/r luma/chroma matching delay bit [2:0] 3...3 variable chroma delay bit [3] 0/1 chroma polarity signed / offset binary bit [4] 0/1 c b (u) sample first / c r (v) sample first bit [5] test bit, set to 0 0 1 0 0 ldb cob envu 66 9 w v digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 dti gain bit [8] 0/1 narrow/wide bandwidth mode 1 5 1 dtico dtiga dtimo inverse matrix 7c 74 9 9 w v w v main picture matrix coefficient ry = mr1m*c b + mr2m*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 0 86 mr1m, mr2m 6c 64 9 9 w v w v main picture matrix coefficient gy = mg1m*c b + mg2m*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 22 44 mg1m, mg2m 5c 54 9 9 w v w v main picture matrix coefficient by = mb1m*c b + mb2m*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 113 0 mb1m, mb2m 78 70 9 9 w v w v side picture matrix coefficient ry = mr1s*c b + mr2s*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 0 73 mr1s, mr2s 68 60 9 9 w v w v side picture matrix coefficient gy = mg1s*c b + mg2s*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 19 37 mg1s, mg2s 58 50 9 9 w v w v side picture matrix coefficient by = mb1s*c b + mb2s*c r bit [9:0] 256/128 ... 255/128 bit [9:0] 256/128 ... 255/128 97 0 mb1s, mb2s color look-up table 000f 16 w h color look-up table : 16 entries, 12 bit wide, the clut registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 000h f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h clut0 clut15 11 16 w h picture frame color 12 bit wide, bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 0 0 0 pfcb pfcg pfcr
ddp 3300 a preliminary data sheet micronas intermetall 25 name default function mode number of bits i 2 c sub address 4c 9 w v digital osd insertion contrast for r (amplitude range: 0 to 255) bit [3:0] 0..13 r amplitude = clutn (drct + 4) 14,15 invalid picture frame insertion contrast for r (ampl. range: 0 to 255) bit [7:4] 0..13 r amplitude = pfcr (pfrct + 4) 14,15 invalid 8 8 drct pfrct 48 9 w v digital osd insertion contrast for g (amplitude range: 0 to 255) bit [3:0] 0..13 g amplitude = clutn (dgct + 4) 14,15 invalid picture frame insertion contrast for g (ampl. range: 0 to 255) bit [7:4] 0..13 g amplitude = pfcg (pfgct + 4) 14,15 invalid 8 8 dgct pfgct 44 9 w v digital osd insertion contrast for b (amplitude range: 0 to 255) bit [3:0] 0..13 b amplitude = clutn (dbct + 4) 14,15 invalid picture frame insertion contrast for b (ampl. range: 0 to 255) bit [7:4] 0..13 b amplitude = pfcb (pfbct + 4) 14,15 invalid 8 8 dbct pfbct picture frame generator 4f 9 w v bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1ff = full frame 0 pfghb 53 9 w v bit [8:0] horizontal picture frame end 0 pfghe 63 9 w v bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled 270 pfgvb 6f 9 w v bit [8:0] vertical picture frame end 56 pfgve enable and priority see under `priority bus' picture frame color see under `color look-up table' scan velocity modulation 62 9 w v video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) 60 4 svg1 svd1 5e 9 w v text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) 60 4 svg2 svd2 5a 9 w v limiter bit [6:0] limit value bit [8:5] not used, set to o0o 100 0 svlim 56 9 w v delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of svmout is the same as for rgbout bit [7:4] coring value bit [8] not used, set to o0o 7 0 svdel svcor
ddp 3300 a preliminary data sheet micronas intermetall 26 name default function mode number of bits i 2 c sub address display controls 52 4e 4a 9 9 9 w v w v w v cutoff red cutoff green cutoff blue 0 0 0 cr cg cb tube and picture measurement 7b 9 w v picture measurement start line bit [8:0] (tml+9)..511 first line of picture measurement 23 pmst 6b 9 w v picture measurement stop line bit [8:0] (pmst+1)..511 last line of picture measurement 308 pmso 7f 9 w v tube measurement line bit [8:0] 0..511 start line for tube measurement 15 tml 25 8 w/r tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 khz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a '1' starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address 32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved 0 pmc tmen pmbw pmen pmwin ofsen 13 16 w/r white drive measurement control bit [9:0] 0..1023 rgb values for white drive beam current measurement bit [10] reserved bit [11] 0/1 rgb values for white drive beam current measurement disabled/enabled 512 0 wdrv ewdm 181d 18 19 1a 1d 1c 1b 8 r measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement mrmin mrmax mrwdr mrcr mrcg mrcb 1e 8 r measurement adc status and fast blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast blank input low / high (static) bit [5] 1 fast blank input negative transition since last read (bit reset at read) bit [7:6] reserved pms
ddp 3300 a preliminary data sheet micronas intermetall 27 name default function mode number of bits i 2 c sub address timing 67 9 w v vertical blanking start bit [8:0] 0..511 first line of vertical blanking 305 vbst 77 9 w v vertical blanking stop bit [8:0] 0..511 last line of vertical blanking 25 vbso 73 9 w v start of black level expander measurement bit [8:0] 0..511 first line of measurement, stop with first line of vertical blanking 30 avst 5f 9 w v bit [8:0] free running field period = (value 4) lines 0 stimp horizontal deflection 7a 9 w v adjustable delay of pll2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog rgb input bit [8:0] 256..+255 8 m s 141 pofs2 76 9 w v adjustable delay of flyback, main sync, csync and analog rgb (relative to pll2) adjust horizontal drive or csync bit [8:0] 256..+255 8 m s 0 pofs3 7e 9 w v adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps 1 m s 120 hpos 5b 9 w/r start of horizontal blanking bit [8:0] 0..511 1 hbst 57 9 w/r end of horizontal blanking bit [8:0] 0..511 48 hbso 6a 6e 72 9 9 9 w v w v w v pll2/3 filter coefficients, 1 of 5 bit code (n bit number set to 1) bit [5:0] proportional coefficient pll3, 2 n1 bit [5:0] proportional coefficient pll2, 2 n1 bit [5:0] integral coefficient pll2, 2 n5 2 1 2 pkp3 pkp2 pki2 15 16 w/r horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in m s (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal pll2 and pll3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] 0/1 reserved, set to '0' bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog rgb input bit [12] 0/1 disable/enable vertical free running mode (field is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] 0/1 internal/external (under vpc control) start of vertical and e/w signal bit [15] 0/1 disable/enable phase shift of display clock 32 0 0 0 0 1 0 0 0 1 hdrv ehpll eflb intrl dubl ebl dcrgb selft dvpr xdefl diska
ddp 3300 a preliminary data sheet micronas intermetall 28 name default function mode number of bits i 2 c sub address output pins 10 8 w/r output pin configuration bit [2:0] pin driver strength, msy and csy 7 = minimum strength 0 = maximum strength bit [[4:3] pin driver strength, fpdat 3 = minimum strength 0 = maximum strength bit [5] 0/1 disable/enable internal resistor for vertical and east/west drive output bit [7:6]] function of csy pin : 00 composite sync signal output 01 25 hz output (field1/field2 signal) 10 no interlace (field 2), output = 0 11 1 mhz horizontal drive clock 0 pstsy pstpri vewxr csym miscellaneous 32 8 w/r fast blank interface mode bit [0] 0 fast blank from fblin pin 1 force internal fast blank signal to high bit [1] 0/1 fast blank active high/low at fblin pin bit [2] 0/1 disable/enable clamping reference for rgb outputs bit [3] 1 full line madc measurement window, disables bit [3] in address 25 bit [4] 0/1 horizontal flyback pulse input active high/low bit [6:5] 0 testbits, set to `0' bit [7] reserved, set to `0' 0 fnfoh fbpol clmpr flmw flpol skmo d
ddp 3300 a preliminary data sheet micronas intermetall 29 4. specifications 4.1. outline dimensions fig. 41: 68-pin plastic leaded chip carrier package (plcc68) weight approx. 4.8 g dimensions in mm 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 2 25 +0.25 43 27 25 +0.25 26 10 9 61 9 44 60 1 x 45 0.457 0.2 0.711 1.9 1.5 4.05 0.1 4.75 0.15 1.27 0.1 2.4 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 1 +0.2 2.4 70043/2 fig. 42: 64-pin plastic shrink dual-inline-package (psdip64) weight approx. 9.0 g dimensions in mm 57.7 0.1 3.8 0.1 1.29 31 x 1.778 = 55.118 0.1 1 0.05 3.2 132 33 64 15 28 4 0.1 0.2 4.8 0.2 0.1 20.1 0.5 0.27 0.1 18 0.1 19.3 0.1 0.457 1.778 0.05 1.9 (1) 03.02.9 5
ddp 3300 a preliminary data sheet micronas intermetall 30 4.2. pin connections and short descriptions nc = not connected lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram in = input out = output pin no. connection pin name type short description plcc 68-pin psdip 64-pin (if not used) 1 32 lv msy out main sync 2 gndd nc not connected 3 31 x fsy in front sync 4 30 x clk5 in 5 mhz clock 5 29 x hout out horizontal drive output 6 28 x vstby stand-by supply voltage 7 27 h out hflb in horizontal flyback input 8 26 gndo vprot in vertical protection input 9 25 gndo safety in safety input 10 24 x scl in i 2 c-bus clock 11 23 x sda in/out i 2 c-bus data 12 22 gndd test in test pin 13 21 x res in reset input 14 20 gndo rsw2 in range switch2, measurement adc 15 19 gndo rsw1 in range switch1, measurement adc 16 18 gndo sense in sense adc input 17 17 x gndm ground, madc input 18 16 lv vert out vertical sawtooth output 19 15 lv ew out vertical parabola output 20 14 gndd nc not connected 21 13 x xref in reference input for rgb dacs 22 gndd nc not connected 23 12 x svmout out scan velocity modulation 24 11 vsupo rout out analog output red 25 10 vsupo gout out analog output green 26 9 vsupo bout out analog output blue 27 8 x gnd o ground, analog backend 28 7 x vsupo supply voltage, analog backend
ddp 3300 a preliminary data sheet micronas intermetall 31 short description type pin name connection pin no. (if not used) psdip 64-pin plcc 68-pin 29 6 x vrd/bcs in dac reference, beam current safety 30 5 gndo rin in analog red input 31 4 gndo gin in analog green input 32 3 gndo bin in analog blue input 33 2 gndo fblin in fast blank input 34 gndo nc not connected 35 1 gndd osd0 in picture bus osd (lsb) 36 64 gndd osd1 in picture bus osd 37 63 gndd osd2 in picture bus osd 38 62 gndd osd3 in picture bus osd 39 61 gndd osd4 in picture bus osd (msb) 40 60 x fpdat in/out deflection data interface to vpc 41 59 gndd pr2 in picture bus priority (msb) 42 58 gndd pr1 in picture bus priority 43 57 gndd pr0 in picture bus priority (lsb) 44 56 gndd c0 in picture bus chroma (lsb) 45 55 gndd c1 in picture bus chroma 46 54 gndd c2 in picture bus chroma 47 53 gndd c3 in picture bus chroma 48 52 gndd c4 in picture bus chroma 49 51 gndd c5 in picture bus chroma 50 50 gndd c6 in picture bus chroma 51 49 gndd c7 in picture bus chroma (msb) 52 48 x vsupd supply voltage, digital circuitry 53 47 x gndd ground, digital circuitry 54 46 x clk20 in 20 mhz system clock input 55 45 gndd y0 in picture bus luma (lsb) 56 44 gndd y1 in picture bus luma 57 43 gndd y2 in picture bus luma 58 42 gndd y3 in picture bus luma 59 41 gndd y4 in picture bus luma
ddp 3300 a preliminary data sheet micronas intermetall 32 short description type pin name connection pin no. (if not used) psdip 64-pin plcc 68-pin 60 40 gndd y5 in picture bus luma 61 39 gndd nc not connected 62 38 gndd y6 in picture bus luma 63 37 gndd y7 in picture bus luma (lsb) 64 36 gndd nc not connected 65 x gndd ground, digital circuitry 66 35 gndd nc not connected 67 34 x vsupp supply voltage, output pin driver 68 33 lv csy out composite sync output 4.3. pin descriptions (pin numbers for plcc68) nc = not connected pin 1 main sync signal output msy (fig. 45) this pin supplies the front end ics with the main horizon- tal sync information, locked to the horizontal flyback. also line number, field even/odd and vertical blanking in- formation is included. pin 3 front sync signal input fsy (fig. 411) this pin gets the front horizontal sync information from the video decoder vpc 32xx. also skew, vertical sync, field even/odd and pal-plus helper line indication is in- cluded. pin 4 5 mhz clock input clk5 (fig. 47) 5 mhz clock required for hout and csy generation during standby mode. pin 5 horizontal drive hout (fig. 413) this open drain output supplies the drive pulse for the horizontal output stage. the gating with the flyback pulse is selectable by software. pin 6 standby supply voltage vstdby in standby mode this pin supplies the horizontal drive cir- cuitry. pin 7 horizontal flyback input hflb (fig. 49) via this pin the horizontal flyback pulse is supplied to the ddp. pin 8 vertical protection input vprot (fig. 49) the vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. during vertical blanking, a signal level of 2.5v is sensed. if a negative edge cannot be detected, the rgb output signals are blanked. pin 9 safety input, safety (fig. 49) this is a three-level input. low level means normal func- tion. at the medium level rgb signals are blanked and at high level rgb signals are blanked and horizontal drive is shut off. pin 10 i 2 c clock input scl (fig. 410) via this pin the clock signal for the i 2 c-bus is supplied. pin 11 i 2 c data input/output sda (fig. 410) via this pin the i 2 c-bus data are written to or read from the ddp. pin 12 test input test (fig. 47) this pin enables factory test modes. for normal opera- tion it must be connected to ground. pin 13 reset input res (fig. 47) a low level on this pin resets the ddp. pin 14,15 range switch for meas. adc rsw1 rsw2 (fig. 414 ) these pins are open drain pulldown outputs. during cut- off measurement both switches are off. during white drive measurement rsw1 is switched off and rsw2 is switched on. during the rest of time both switches are on. pin 16 measurement adc input sense (fig. 49) this is the input of the analog to digital converter for the picture and tube measurement. three ranges of mea- surement are selectable with rsw1 and rsw2.
ddp 3300 a preliminary data sheet micronas intermetall 33 pin 17 measurement adc reference input mgnd this is the ground reference for the measurement a/d converter. pin 18 vertical sawtooth output vert (fig. 415) this pin supplies the drive signal for the vertical output stage. the drive signal is generated with 15-bit precision by the fast processor in the vpc. the analog voltage is generated by a 4 bit current-dac with external resistor and uses digital noise shaping. pin 19 east-west parabola output ew (fig. 415) this pin supplies the parabola signal for the east-west correction. the drive signal is generated with 15 bit pre- cision by the fast processor in the vpc. the analog voltage is generated by a 4 bit current-dac with external resistor and uses digital noise shaping. pin 20 nc pin 21 dac current reference xref (fig. 416) external reference resistor for dac output currents, typi- cal 10 k w to adjust the output current of the d/a convert- ers. (see recommended operating conditions). this re- sistor has to be connected to analog ground as closely as possible to the pin. pin 23 scan velocity modulation output svmout (fig. 412) this output delivers the analog svm signal. the d/a converter is a current sink like the rgb d/a converters. at zero signal the output current is 50% of the maximum output current. pin 26,25,24 analog rgb output rout , gout , bout (fig. 412) this are the analog red/green/blue outputs of the back- end. the outputs are current sinks with a maximum cur- rent of 8 ma. pin 27 ground, analog backend gndo pin 28 supply voltage, analog backend vsupo pin 29 dac reference decoupling/beam current safety vrd/bcs (fig. 416) via this pin the dac reference voltage is decoupled by an external capacitor. the dac output currents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. a decoupling capaci- tor of 3.3 m f||100 nf is required. pin 32,31,30 analog rgb input rin , gin , bin (fig. 49) these pins are used to insert an external analog rgb signal, e.g. from a scart connector which can by switched to the analog rgb outputs with the fast blank signal. the analog backend provides separate bright- ness and contrast settings for the external analog rgb signals. pin 33 fast blank input fblin (fig. 49) this pin is used to switch the rgb outputs to the external analog rgb inputs. pin 34 nc pin 35...39 picture bus osd osd0...osd4 (fig. 411) the picture bus osd lines carry the digital osd color data. they are used as address for the color lookup table. pin 40 deflection data interface fpdat (fig.46 ) this is the bidirectional interface to the fast processor in the vpc for deflection data calculation. pin 41,42,43 picture bus priority pr2pr0 (fig. 46) the picture bus priority lines carry the digital priority selection signals. the priority interface allows digital switching of up to 8 sources to the backend processor. switching for different sources is prioritized and can be done from pixel to pixel. pin 44...51 picture bus chroma c0...c7 (fig. 411) the picture bus chroma lines carry the digital chromi- nance data. the data are sampled at 20.25 mhz and multiplexed c b c r . pin 52 supply voltage, digital circuitry vsupd pin 53 ground, digital circuitry gndd pin 54 main clock input clk20 (fig. 48) this is the 20.25 mhz main system clock that is used by all circuits in a high-end vpc system. pin 55...60, 62, 63 picture bus luma l0...l7 (fig. 411) the picture bus luma lines carry the digital luminance data. the data are sampled at 20.25 mhz. pin 61 nc pin 64 nc pin 65 ground, digital circuitry input reference gndd pin 66 nc pin 67 supply voltage, output pin driver vsupp this pin is used as supply for the following digital output pins : csy, msy. pin 68 composite sync output csy (fig. 45) this output supplies a standard composite sync signal that is compatible to the analog rgb output signals.
ddp 3300 a preliminary data sheet micronas intermetall 34 4.4. pin configuration the pin drawings show all signals for the 68-pin plcc package (fig. 43) and for the 64-pin shrink dip pack- age (fig. 44) 44 60 61 9 10 27 26 43 1 fig. 43: pinning of the ddp 3300 a in plcc68 package msy nc fsy clk5 hout vstby hflb vprot safety scl sda test res rsw2 rsw1 sense gndm vert ew nc xref nc svmout rout gout bout gndo vsupo vrd/bcs rin gin bin fblin nc osd0 osd1 osd2 osd3 osd4 fpdat pr2 pr1 pr0 c0 c1 c4 c5 c6 c7 c2 c3 vsupd gndd clk20 y0 y1 y2 y3 y4 y5 nc y6 y7 nc gndd nc vsupp csy ddp 3300 a
ddp 3300 a preliminary data sheet micronas intermetall 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 fig. 44: pinning of the ddp 3300 a in psdip64 package ddp 3300 a msy nc fsy clk5 hout vstby hflb vprot safety scl sda test res rsw2 rsw1 sense gndm vert ew nc xref svmout rout gout bout gnd o vsupo vrd/bcs rin gin bin fblin osd0 osd1 osd2 osd3 osd4 fpdat pr2 pr1 pr0 c0 c1 c4 c5 c6 c7 c2 c3 vsupd gndd clk20 y0 y1 y2 y3 y4 y5 y6 y7 nc nc vsupp csy
ddp 3300 a preliminary data sheet micronas intermetall 36 4.5. pin circuits fig. 45: output pins msy, csy p n gndd v supp n p n fig. 46: i/o pins pr0, pr1, pr2, fpdat fig. 47: input pins test, res , clk5 fig. 48: input pins clk20 pp nn v supo gndo bias fig. 49: input pins safety, vprot, hflb, fblin, rin, bin, gin, sense n p n fig. 410: i/o pins scl, sda fig. 411: input pins c[7:0], l[7:0], osd[4:0], fsy p n v supd gndd gndo v supo bias n n fig. 412: analog output pins rout, gout, bout, svmout v stdby gndo fig. 413: output pin hout n mgnd fig. 414: output pins rsw1, rsw2 n
ddp 3300 a preliminary data sheet micronas intermetall 37 pp v supo fig. 415: output pins for vert and e/w gndd + int. ref. voltage ref. current v supo gndo vrd/bcs xref fig. 416: input pins xref and vrd/bcs
ddp 3300 a preliminary data sheet micronas intermetall 38 4.6. electrical characteristics 4.6.1. absolute maximum ratings symbol parameter pin name min. max. unit t a ambient operating temperature 0 65 c t s storage temperature 40 125 c v sup supply voltage, all supply inputs 0.3 6 v v i input voltage, all inputs 0.3 v sup 0.3 v v o output voltage, all outputs 0.3 v sup 0.3 v stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. 4.6.2. recommended operating conditions symbol parameter pin name min. typ. max. unit v sup supply voltages, all supply pins (but output pin driver supply) 4.75 5.0 5.25 v v supp output pin driver supply voltage vsupp 3.0 5.0 5.25 v f sys clock frequency clk20 20.25 mhz r xref rgb dac current defining resistor xref 9.5 10 10.5 k w ns vdd negative slope of vdd (power down) vsupd 0.2 v/ m s 4.6.3. characteristics min./max. values at: t a 0 to 65 c, v sup 4.75 to 5.25 v, r xref 10 k w, f 20.25 mhz typical values at: t c 60 c, v sup 5 v, r xref 10 k w, f 20.25 mhz 4.6.4. general characteristics symbol parameter pin name min. typ. max. unit i vsupo current consumption analog backend vsupo 58 70 85 ma i vsupd current consumption digital processing vsupd 70 ma i vsupp current consumption output pin driver vsupp tbd ma i vstdby current consumption standby circuit vstdby 3 ma p tot total power dissipation 0.74 w i l input and output leakage current (if not otherwise specified) 1.0 m a
ddp 3300 a preliminary data sheet micronas intermetall 39 4.6.5. bus inputs: luma, chroma, osd, front sync (see fig. 417) symbol parameter pin name min. typ. max. unit test conditions v il input low voltage y[0..7] c[0 7] 0.8 v v ih input high voltage c[0 .. 7] osd[0:4] fsy 1.5 v t is input setup time fsy 7 ns t ih input hold time 6 ns data inputs main clock t is t ih y,c,rgb,fsync fig. 417: picture bus input timing 4.6.6. 20.25 mhz main clock input, internally ac coupled (see fig. 418) symbol parameter pin name min. typ. max. unit test conditions v it input trigger level clk20 2.1 2.5 2.9 v f f f main clock frequency 10 20.25 24 mhz v f midc f main clock input dc volt- age 1.0 3.5 v v f miac f m clock input ac voltage (pp) 0.8 2.5 v t f mih t f mil f m clock input high/low ratio 0.9 1.0 1.1 t f mihl f m clock input high to low transition time 0.15 f f m t f milh f m clock input low to high transition time 0.15 f f m t f milh 0 v v f midc v f miac t f mihl t f mih t f mil dvss fig. 418: main clock input
ddp 3300 a preliminary data sheet micronas intermetall 40 4.6.7. 5 mhz clock input (see fig. 419) symbol parameter pin name min. typ. max. unit test conditions v il input low voltage clk5 2.0 v v ih input high voltage 3.1 v t f signal fall time 60 ns t r signal rise time 60 ns f ck5 clock frequency 4 6 mhz t r t high t low v ih v il fig. 419: 5 mhz clock input t f 4.6.8. i 2 c-bus interface symbol parameter pin name min. typ. max. unit test conditions v il input low voltage sda scl 1.5 v v ih input high voltage scl 3.0 v v ol output low voltage 0.4 0.6 v v i l = 3ma i l = 6ma i ol output low current 10 ma v ih input capacitance tbd pf t f signal fall time 300 ns c l = 400 pf t r signal rise time 300 ns c l = 400 pf f scl clock frequency scl 0 400 khz t low low period of scl 1.3 m s t high high period of scl 0.6 m s t su data data set up time to scl high sda 100 ns t hd data data hold time to scl low 0 0.9 m s 4.6.9. reset input, test input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage res test 2.0 v v ih input high voltage test 3.1 v
ddp 3300 a preliminary data sheet micronas intermetall 41 4.6.10. serial deflection interface symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage fpdat 0.5 v i ol = 8 ma, strength 3 i ol = 6 ma, strength 2 i ol = 4 ma, strength 1 i ol = 2 ma, strength 0 v oh output high voltage 1.8 2.0 2.5 v i ol < 10 m a c load = 71pf t oh output hold time 6 tbd ns c load = 71pf i pl = 8.4 ma t odl output delay time 35 ns c load = 71pf i pl = 8.4 ma i pl output pull-up current 1.2 1.5 1.8 ma v ol = 0v v il input low voltage 0.8 v v ih input high voltage 1.5 v t is input setup time 7 ns t ih input hold time 5 ns v ih v il input 20 mhz clock t is t ih v ol t odl v ohtri t oh t oh t odl fig. 420: serial deflection interface output
ddp 3300 a preliminary data sheet micronas intermetall 42 4.6.11. priority bus input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage pr[2:0] 0.8 v v ih input high voltage 1.5 v t is input setup time 7 ns t ih input hold time 5 ns 4.6.12. horizontal flyback input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage hflb 1.8 v v ih input high voltage 2.6 v v ihst input hysteresis 0.1 v psrr hf power supply rejection ra- tio of trigger level 0 db f = 20 mhz psrr mf power supply rejection ra- tio of trigger level 20 db f < 15 khz psrr lf power supply rejection ra- tio of trigger level 40 db f < 100 hz t pid internal delay 12 ns slew rate 500 mv/ns swing 1 v pp 4.6.13. main sync output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage msy 0.2 0.4 v i ol = 1.6 ma, strength 7 v oh output high voltage v supp 0.4 v supp v i ol = 1.6ma, strength 7 t oh output hold time 6 14 tbd ns c load = 70pf t od output delay time 35 ns c load = 70pf i ol output current 10 10 ma driver imp. = 0
ddp 3300 a preliminary data sheet micronas intermetall 43 4.6.14. combined sync output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage csy 0.4 v i ol = 1.6 ma strength 7 v oh output high voltage v supp 0.4 v supp v i ol = 1.6 ma strength 7 t ot output transition time 10 20 ns c load = 30 pf i ol output current 10 10 ma driver imp . = 0 4.6.15. horizontal drive output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage hout 0.4 v i ol = 10 ma v oh output high voltage (open drain stage) 8 v external pull-up resistor t of output fall time 8 20 ns c load = 30pf i ol output low current 10 ma 4.6.16. vertical protection input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage vprot 1.8 v v ih input high voltage 2.6 v v ihst input hysteresis 0.1 v 4.6.17. vertical safety input symbol parameter pin name min. typ. max. unit test conditions v ila input low voltage a safety 1.8 v v iha input high voltage a 2.6 v v ilb input low voltage b 3.1 v v ihb input high voltage b 3.9 v v ihst input hysteresis a and b 0.1 v t pid internal delay 100 ns
ddp 3300 a preliminary data sheet micronas intermetall 44 4.6.18. vertical and east / west drive output symbol parameter pin name min. typ. max. unit test conditions v ol output voltage low ew vert 0 v r load = 6800 r xref = 10 k w v oh output voltage high 2.82 3 3.2 v r load = 6800 r xref = 10 k w i dacn full scale dac output current 415 440 465 m a vo = 0v r xref = 10 k w psrr power supply rejection ratio 20 db 4.6.19. sense a/d converter input symbol parameter pin name min. typ. max. unit test conditions v i input voltage range sense 0 v sup v v i255 input voltage for code 255 1.4 1.54 1.7 v read cutoff blue register c 0 digital output for zero input 16 lsb offset check, read cutoff blue register r i input impedance 1 m w range switch outputs r on output on resistance rsw1 rsw2 50 w i ol = 10 ma i max maximum current rsw2 15 ma i leak leakage current 600 na rsw high impedance c in input capacitance tbd pf
ddp 3300 a preliminary data sheet micronas intermetall 45 4.6.20. analog rgb and fb inputs symbol parameter pin name min. typ. max. unit test conditions v rgbin external rgb inputs voltage range rin gin bin 0.3 1.1 v v rgbin nominal rgb input voltage peak-to-peak bin 0.5 0.7 1.0 v pp scart spec: 0.7 v 3 db v rgbin rgb inputs voltage for maxi- mum output current 0.44 contrast setting: 511 rgb inputs voltage for maxi- mum output current 0.7 contrast setting: 323 rgb inputs voltage for maxi- mum output current 1.1 contrast setting: 204 c rgbin external rgb input coupling capacitor 15 nf clamp pulse width 3.1 m s c in input capacitance 13 pf i il input leakage current 0.5 0.5 m a clamping off, v in 0.3..3 v v clip rgb input voltage for clipping current 2 v v clamp clamp level at input 40 60 80 mv clamping on v inoff offset level at input 10 10 mv extrapolated from v in = 100 mv and 200 mv v inoff offset level match at input 10 10 mv extrapolated from v in = 100 mv and 200 mv r clamp clamping-on-resistance 140 w v fbloff fblin low level fblin 0.5 v v fblon fblin high level 0.9 v v fbltrig fast blanking trigger level typical 0.7 t pid delay fast blanking to rgb out from midst of fblintransi- tion to 90% of rgb out transi- tion 8 15 ns internal rgb = 3.75 ma full scale int. brightness = 0 external brightness = 1.5 ma (full scale) rgbin = 0 v fbloff = 0.4 v v fblon = 1.0 v rise and fall time = 2 ns difference of internal delay to external rgbin delay 5 +5 ns switch-over-glitch 0.5 pas switch from 3.75 ma (int) to 1.5 ma (ext)
ddp 3300 a preliminary data sheet micronas intermetall 46 4.6.21. analog rgb outputs, d/a converters symbol parameter pin name min. typ. max. unit test conditions internal rgb signal d/a converter characteristics resolution rout gout 10 bit i out full scale output current gout bout 3.6 3.75 3.9 ma r ref = 10 k w i out differential nonlinearity 0.5 lsb i out integral nonlinearity 1 lsb i out glitch pulse charge 0.5 pas ramp signal, 25 w output termination i out rise and fall time 3 ns 10% to 90%, 90% to 10% i out intermodulation 50 db 2/2.5mhz full scale i out signal to noise +50 db signal: 1mhz full scale bandwidth: 10mhz i out matching rg, rb, gb 2 2 % r/b/g crosstalk one channel talks two channels talk 46 db passive channel: i out =1.88 ma crosstalksignal: 125mhz 375ma rgb input crosstalk from ex- ternal rgb one channel talks two channels talk three channels talk 50 50 50 db db db 1 . 25 mhz , 3 . 75 ma pp internal rgb brightness d/a converter characteristics resolution rout gout 9 bits i br full scale output current relative gout bout 39.2 40 40.8 % ref to max. digital rgb i br full scale output current absolute 1.5 ma i br differential nonlinearity 0.5 lsb i br integral nonlinearity 1 lsb i br match rg, rb, gb 2 2 % i br match to digital rgb rr, gg, bb 2 2 % external rgb voltage/current converter characteristics resolution rout gout 9 bits i exout full scale output current rel- ative gout bout 96 100 104 % ref. to max. digital rgb v in = 0.7 v pp , con- trast = 323 full scale output current absolute 3.75 ma same as digital rgb cr contrast adjust range 16:511
ddp 3300 a preliminary data sheet micronas intermetall 47 test conditions unit max. typ. min. pin name parameter symbol gain match rg, rb, gb rout gout bout 2 2 % measured at rgb out- puts v in = 0.7 v, contrast = 323 gain match to rgbdacs rr, gg, bb 3 3 % measured at rgb out- puts v in = 0.7 v, contrast = 323 r/b/g input crosstalk one channel talks two channels talk 46 db passive channel: v in = 0.7v, contrast = 323 rgb input crosstalk from internal rgb one channel talks two channels talk tree channels talk 50 db crosstalk signal: 1.25 mhz, 3.75 ma pp rgb input noise and distortion 50 db v in =0.7 v pp at 1 mhz contrast = 323 bandwidth: 10 mhz rgb input bandwidth 3db 10 15 mhz v in = 0.7 v pp , contrast =323 rgb input thd 50 40 db db input signal 1 mhz input signal 6 mhz v in = 0.7 v pp contrast =323 differential nonlinearity of contrast adjust 1.0 lsb v in = 0.44v integral nonlinearity of contrast adjust 7 lsb v rgbo r,g,b output voltage 1.0 0.3 v referred to v supo r,g,b output load resis- tance 100 w ref. to v supo v outc rgb output compliance 1.5 1.3 1.2 v ref. to v supo sum of max. current of rgbdacs and max. current of int. brightness dacs is 2% degraded external rgb brightness d/a converter characteristics resolution rout gout 9 bits i exbr full scale output current relative gout bout 39.2 40 40.8 % ref to max. digital rgb full scale output current ab- solute 1.5 ma differential nonlinearity 0.5 lsb integral nonlinearity 1 lsb matching rg, rb, gb 2 2 % matching to digital rgb rr, gg, bb 2 2 %
ddp 3300 a preliminary data sheet micronas intermetall 48 test conditions unit max. typ. min. pin name parameter symbol rgb output cutoff d/a converter characteristics resolution rout gout 9 bits i cut full scale output current rel- ative gout bout 58.8 60 61.2 % ref to max. digital rgb i cut full scale output current absolute 2.25 ma i cut differential nonlinearity 0.5 lsb i cut integral nonlinearity 1 lsb i cut match to digital rgb rr, gg, bb 2 2 % rgb output ultrablack d/a converter characteristics resolution rout gout 1 bits i ub full scale output current relative gout bout 19.6 20 20.4 % ref to max. digital rgb full scale output current absolute 0.75 ma match to digital rgb rr, gg, bb 2 2 % 4.6.22. dac reference, beam current safety symbol parameter pin name min. typ. max. unit test conditions v dacr ef dacref. voltage vrd/bcs 2.38 2.50 2.67 v dacref. output resistance vrd/bcs 18 25 32 k w v xref dacref. voltage bias current generation xref 2.25 2.34 2.43 v 4.6.23. scan velocity modulation output symbol parameter pin name min. typ. max. unit test conditions svm d/a converter characteristics resolution svmout 8 bit i out full scale output current 1.55 1.875 2.25 ma i out differential nonlinearity 0.5 lsb i out integral nonlinearity 1 lsb i out glitch pulse charge 0.5 pas ramp, output line is ter- minated on both ends with 50 ohms i out rise and fall time 3 nsec 10% to 90%, 90% to 10%
ddp 3300a micronas intermetall 49 fig. 51: application diagram
ddp 3300a preliminary data sheet micronas intermetall 50
ddp 3300 a preliminary data sheet micronas intermetall 51
ddp 3300 a preliminary data sheet micronas intermetall 52 5. data sheet history 1. advance information: addp 3300 ao, feb. 9, 1996, 6251-421-1ai. first release of the advance information. 2. preliminary data sheet: addp 3300 ao, june 19, 1996, 6251-421-1pd. first release of the preliminary data sheet. micronas intermetall gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@intermetall.de internet: http://www.intermetall.de printed in germany order no. 6251-421-1pd all information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas intermetall gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. reprinting is generally permitted, indicating the source. how- ever, our prior consent must be obtained in all cases.
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